Browse Prior Art Database

Enhanced Transverse Via/Transtrip

IP.com Disclosure Number: IPCOM000039214D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Gow, J [+details]

Abstract

This article relates to packaging semiconductor chips on a ceramic carrier, combining punch-and-fill techniques of multilayer ceramic [1] carrier fabrication with transverse via/transtrip [2] ceramic carrier technology, allowing more degrees of output freedom. A multilayer ceramic chip carrier package (exploded view shown in Fig. 1) is fabricated by stacking a set of personalized ceramic greensheets (sheets before firing) together. Each sheet in the stack is personalized by silk screen or photolithographic techniques to form conductor lines and a via grid of holes is punched and filled with a metallic paste to interconnect the layers. The set is subsequently fired, causing the sheets to cure and fuse together, forming a multilevel wiring semiconductor chip carrier.