Testcase Pattern Generation for Design Verification Using a System Level Simulator
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Well-known logic design techniques employing the level sensitive scan design (LSSD) have long been utilized to verify manufacturing processes. However, the major challenge in the development of any new processor is the creation of a methodology which will validate the processor's overall algorithmic design. This article describes one (Image Omitted) method for providing system level testcase patterns to verify a logic design prior to initial hardware build. Design verification requires validation of both the overall system operation (does the system perform correctly for all operations?) and the individual logic design (does this set of Boolean equations correctly represent the desired function?).