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Alternative Method of Making Self-Aligned MESFET Transistors

IP.com Disclosure Number: IPCOM000039236D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Nguyen, TN Rubloff, GW [+details]

Abstract

This publication describes a method for fabricating self-aligned gate MESFETs using sidewall spacers and with a broader metallurgy choice and a single contact metallization step. Its main features are that the source and drain implant anneal at high temperatures is done prior to the gate, source, and drain metallization. This removes the requirement of a high-temperature gate material for self-aligned transistors and allows the use of many low-temperature metals that were not possible before. Also, the metal contacts to the gate, source, and drain are fabricated in a single step; in contrast, standard self-aligned FET processes normally require two steps, one for gate formation as a self- alignment mask and a second for contact deposition. (Image Omitted) The key steps of the method are explained below: 1. Fig.