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Using a Reduced Instruction Set Computer Level Interrupt to Patch S/370 Emulation Logic

IP.com Disclosure Number: IPCOM000039251D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Bechdel, JF Kalla, RN Mitchell, JA [+details]

Abstract

Logic errors which are discovered during bring up and debug phases of processor development delay the processor debug. The establishment of a temporary logic patch permits logic errors to be bypassed so that hardware debug can continue. A description of the patch methodology is described below. IBM has developed a series of minicomputers which implement an emulation methodology to allow the full System/370 architecture to be run on reduced instruction set computer (RISC)-based microprocessors. The microprocessors are utilized as the instruction processing and floating point units. A separate microcode-driven very large-scale integrated (VLSI) microprocessor, an emulator assist processor (EAP), uses a combination of hardware and software interfaces to facilitate efficient emulation of the S/370 architecture.