Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
This article describes a structure for a CMOS operational amplifier in which a biasing device and differential pair devices are placed in separate N-wells on a P substrate. By using two N-wells, the common mode range and the small signal gain of the amplifier area increased beyond that of a one N-well design. Fig. 1 shows an input stage for a typical CMOS differential AMPLIFIER. DEVICE T1 (P AND N INDICATE THE TYPES OF DEVICES) IS A CURRENT source providing a bias current to the differential pair T2A and T2B, respectively. The differential signal, Vdif, is amplified and converted to a single-ended signal, Vout . The gain of the circuit may be expressed as follows: Av = gm2 / (go2+go4) (1) (Image Omitted) where gm2 = transconductance of T2 go = small signal output conductance.