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Method of Preparing CMOS Chips for Gate Oxide Defect Analysis and of Controlling Rox and Polysilicon Structures

IP.com Disclosure Number: IPCOM000039317D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Mayer-Roob, M Steiner, D [+details]

Abstract

The gate oxide of CMOS chips is covered with polysilicon gates which are laterally framed by what is known as a spacer oxide. This first layer of electrical wiring is covered with a layer of phosphor silicate glass (PSG), on top of which the metallization layers are built. For preparing the chip for analysis, first of all the metal layers and appropriate insulating layers are removed by wet and dry etching. Then the chip is glued flat to a special specimen holder and finally polished on a thick-pile cotton cloth, covered with a thick layer of an aqueous solution of silicates, until the polysilicon has been reached. The remaining polysilicon is removed by NaOH etching which bares the gate oxide areas surrounded by the space oxide.