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Method for Testing Embedded Shift Register in a DRAM Chip

IP.com Disclosure Number: IPCOM000039330D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Fitzgerald, BF Thoma, EP Whittaker, DR [+details]

Abstract

Using data written into an array as a test on the functionality of the refresh address counter is reported. Many dynamic random-access memories (DRAMs) have a refresh address counter on the chip which is usually architected as a shift register (SR). Because the SR is usually an integral part of the addressing circuits, it is not accessible to the outside of the chip, which makes a functionality test of the refresh counter circuit difficault and time consuming. The conventional method of testing the refresh address counter circuits has been to write the memory array to a high level (1's) and then pause to force the SR to refresh the array. After many refresh cycles have taken place, the array is read out and scanned for unique fail patterns related to the refresh address counter.