High-Level Shapes Checking Language
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
The high level language ground rules and checking procedure discussed in this article defines and outlines the methodology used to check for illegal shapes early in the integrated circuit (IC) fabrication process. This IC shapes checking procedure allows for the timely flagging (Image Omitted) of error conditions found during the design layout phase of IC fabrication. Other advantages are: 1) Allows engineers to more precisely define the ground rules for legal shapes. 2) Shortens turnaround time for producing a ground rules checking deck. 3) Increases manufacturing yields by flagging error conditions early. Fig. 1 shows the flow diagram for this IC fabrication procedure. Fig. 2 shows the key concepts. KEY WORDS and CONCEPTS of the methodology are: 1.