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Program for Generating a Fault MODEL of a Differential Cascode Emitter-Coupled LOGIC Tree Disclosure Number: IPCOM000039334D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01

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Leet, DG [+details]


A program is described which defines a near minimum number of logic blocks required for a fault model of a differential cascode emitter- coupled logic (CECL) tree and defines those stuck faults required to generate a complete DC test for the tree. The basic functional unit of a CECL circuit is a differential pair (Image Omitted) of bipolar transistors. The next higher level of CECL circuit complexity is the tree. A simple tree for computing the function f(DCBA) = (0000,0x10,100x,x11x) is shown in Fig. 1. Note that a key behavioral characteristic of a tree is that there is one and only one current path to one of its two outputs for each stimulus.