Multiple Imaging of a Single Positive Resist Layer

Publishing Venue

IBM

Related People

Robinson, JA: AUTHOR

Abstract

This article describes a technique allowing consecutive masking levels to be done in a single layer of positive photoresist using the SFET process to fabricate VLSI chips. Upon the completion of a photo level in the manufacture of VLSI chips, a resist removal step is normally performed. By simply man (Image Omitted) ipulating the sequence of some process steps, a situation can be created which allows a single resist layer to be used for two or more sequential masking levels. Multiple exposure of a single resist layer is predicated upon two conditions being satisfied. First, resist photosensitivity must be maintained from one photo level to the next. Secondly, the photo steps must be consecutive.

Multiple Imaging of a Single Positive Resist Layer

This article describes a technique allowing consecutive masking levels to be done in a single layer of positive photoresist using the SFET process to fabricate VLSI chips. Upon the completion of a photo level in the manufacture of VLSI chips, a resist removal step is normally performed. By simply man

(Image Omitted)

ipulating the sequence of some process steps, a situation can be created which allows a single resist layer to be used for two or more sequential masking levels. Multiple exposure of a single resist layer is predicated upon two conditions being satisfied. First, resist photosensitivity must be maintained from one photo level to the next. Secondly, the photo steps must be consecutive. The technique is restricted to consecutive masking levels where areas exposed and opened by a preceding photo step need not be covered during subsequent process steps. Multiple imaging of a single positive resist layer omits the extraneous steps of resist removal and reapply (a cost saving), and a self-aligning feature in areas opened by one mask step and re-exposed in a sub sequent mask step is offered. The technique also eliminates a critical process problem of resist trapping. Capacitance tailoring utilizing a single positive photoresist layer is shown in Fig. 2 through Fig. 7 as an example of the utility of this process. Capacitance tailoring is the design and control of different within-chip capacitance. The need for different within-chip capacitance aris...