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Multiple Imaging of a Single Positive Resist Layer

IP.com Disclosure Number: IPCOM000039336D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Robinson, JA [+details]

Abstract

This article describes a technique allowing consecutive masking levels to be done in a single layer of positive photoresist using the SFET process to fabricate VLSI chips. Upon the completion of a photo level in the manufacture of VLSI chips, a resist removal step is normally performed. By simply man (Image Omitted) ipulating the sequence of some process steps, a situation can be created which allows a single resist layer to be used for two or more sequential masking levels. Multiple exposure of a single resist layer is predicated upon two conditions being satisfied. First, resist photosensitivity must be maintained from one photo level to the next. Secondly, the photo steps must be consecutive.