Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
This article describes a communication adapter which operates as an interface between a host processor and a display terminal device wherein parameters required to process various commands sent from the host processor are stored in a random-access memory (RAM) in the communication adapter, and a decode and sequence circuit in the communication adapter decodes the received command and fetches the parameters for processing the received command from the RAM to a common register. The figure shows a host processor 1, a communication adapter 2 and a display terminal device 11. The communication adapter 2 includes a receive circuit 3, a decode and sequence circuit 4, a transmission buffer 5, an address register 6, a count register 7, RAM 8 and a transmission circuit 9.