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Differential Cmos Clock Driver With Controlled Slew-Rate

IP.com Disclosure Number: IPCOM000039348D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Verhaeghe, M [+details]

Abstract

This circuit generates from a single external master clock a clock and its complementary clock fully synchronized and allows the control of the rising time and the fall time of the outputs. It is based on a differential stage driving two symmetrically controlled current generators working in opposition and loading capacitors. The figure describes in detail the circuit: T1, T1B, , T4, T4B, T6, T6B, TS are N Mos transistors and T2, T2B, T3, T3B, T5, T5B are PMos transistors. Transistor TS is the current source; the current IS is controlled by the bias voltage applied to the gate of TS . Transistors T1 and T1B comprise the differential stage; T2 and T2B are the active loads. Transistors T3B, T5B, T3, T5 are current sources mirrored from T2and T2B . Transistors T4, T4B, T6, T6B are also current mirrors.