Simultaneous Busy Channel Monitor
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
The present invention is a device to measure the number of simultaneously busy channels in a computer system. It is useful to know the distribution of the number of simultaneously busy channels when designing memory and channel bus bandwidth. This information may be obtained by sampling the state of all channels (48 on the present IBM 3090 system). Each sample is a 48-bit binary vector. Counting the number of "1" bits in each sample vector produces the distribution of the number of channels that are busy at the same time. The hardware implementation of the above solution for a sampling rate of approximately 200,000 times per second is shown in the figure.