Novel Bus Reconfiguration Scheme With Spare Lines
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
As the complexity of chips increases, the metal wiring becomes a major yield detractor in chip manufacturing. It is a serious concern for very large chip or wafer scale integration. Part of the problem is solved by circuit or functional island redundancy since such redundancy schemes provide redundancy for the internal wiring of the redundant circuit or island. But the intercircuit or interisland wiring also needs to be fault-tolerant in order to get reasonable yields. To be efficient, a bus reconfiguration scheme must be able to repair not only opens or "stuck at" faults on single lines but also shorts between adjacent lines since this kind of failure is frequent in VLSI.