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Transistor-Coupled Cts Memory Cell

IP.com Disclosure Number: IPCOM000039369D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

A high density alternative to the Harper PNP cell has been proposed which eliminates bitline leakage. It is a transistor-coupled complementary-transistor switch (TCCTS) memory cell which is essentially a Harper PNP cell with the I/O NPN device collectors shorted to their bases. (Image Omitted) Harper PNP cells have been widely used in bipolar memory arrays since fast and dense arrays may be designed and no Schottky barrier diodes (SBD) are needed. When the cells are designed to operate in saturation, they become tightly coupled to the bit lines through read/write transistors operating in the inverse mode. The read/write transistors of the ON sides of the cells are always conducting. There are disadvantages to the foregoing couplings: 1.