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Extended Series Gatings With Complementary Emitter-Coupled Logic Circuits

IP.com Disclosure Number: IPCOM000039380D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

A method is proposed to have extended logic performed within power supply voltages in semiconductor devices. The proposal involves circuitry based upon PNP transistors. In previous work a technique allowed for infinite extension of series gatings in emitter-coupled logic circuits. This was accomplished by shifting the top voltage of a current path down to the bottom level with a PNP mirror at the top and an NPN mirror at the bottom. With such an arrangement logic is realized in the upward path by NPN switches. In this proposal it is suggested that as the voltage level is being shifted downward that PNP transistor switches also be used to perform additional logic functions along the chain of series gatings. The circuitry is shown for a 9-way NAND gate in a 3-level cascade technology. The circuitry assumes signal swings of 0.