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Hardware Circuitry for Implementing a Carrier Sense Multiple Access Collision Detect Bus Structure Disclosure Number: IPCOM000039405D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

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Belyeu, SM McNeill, AB Reid, BM Troop, WC [+details]


This article describes a circuit arrangement that allows a microprocessor-based system to interface to a carrier sense multiple access/collision detect (CSMA/CD) bus structure. An implementation of a CSMA/CD bus to control an automotive vehicle's stereo and air conditioning systems is called an entertainment and comfort (E&C) bus. The circuit arrangement disclosed herein consists of five sections as illustrated in the drawing in block diagram. The sections are as follows: (1)The microprocessor-based system (2) The E&C wake-up circuits (3) The E&C bus driver circuits (4) The E&C interface isolation control circuits (5) The hardware collision detection circuits (6) The E&C bus The microprocessor system 1 controls the transmission and reception of data messages over the E&C bus 6.