Browse Prior Art Database

Pipeline Control in Pre-Norm Logic

IP.com Disclosure Number: IPCOM000039408D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Kania, MJ Rickert, JS [+details]

Abstract

This article describes pipelining of pre-normalization of floating-point numbers in the Hex Fraction Chip (HFRAC) of the Engineering Scientific Accelerator card (ESA). The ESA performs Hex floating-point arithmetic. The HFRAC Chip contains the arrays which hold floating-point data, perform floating-point arithmetic exponent calculations, and perform normalization, of which there are two types: (Image Omitted) 1. Pre-normalization: shifting left of fractions of operands read out of array to eliminate leading zeroes. Exponent is updated by subtracting the shift amount from its value. 2. Post-normalization: shifting left of fractions of arithmetic results to eliminate leading zeroes before writing results into arrays.