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New Latch Family for Mesfet Gate Arrays in DCFL Logic Disclosure Number: IPCOM000039412D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

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Boudon, G Mollier, P Rivier, M Rousseau, B [+details]


Latches represent a large portion of the silicon area in logic chips. It is especially true for DCFL gate arrays where latches require a large number of devices. Fig. 1 shows the schematic of a shift register latch which uses 44 devices when built with conventional NOR gates (12 NOR 2 way plus 5 inverters). This scheme has two disadvantages which are in contradiction with the objective - speed - and present capabilities - yield - of the GaAs technology: long delay path and large number of devices. It is therefore essential to design new schemes with shorter delay paths and fewer devices. This proposal achieves these two objectives. The circuit disclosed hereafter (see Fig. 2) is compatible with a GaAs gate array with enhancement/depletion devices. All the devices of the same type have the same size.