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IP.com Disclosure Number: IPCOM000039437D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Malaviya, SD [+details]

Abstract

The semiconductor process produces a compact, symmetrical NPN transistor plus a P-base resistor ready for first-level metal using only four masks. By using four additional masks in a modification to the process, a submicron-channel, field-effect transistor (FET) with a lightly-doped drain can be included in the structure. The basic structure of the NPN transistor is shown in idealized form in Fig. 1, where the N+ substrate 1 is processed to form a stud- shaped structure. P+ region 26 forms the base with N+ regions 25 and 27 forming the emitter and collector of the transistor. Metal regions 28 and 29 serve as connections to the emitter and collector. Regions 23 and 24 are insulating layers. The structure for the FET (not shown in Fig. 1) is very similar physically to that of Fig.