Pipeline Prefetch Detector
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Many high speed processors have a pipelined architecture where macro instructions are prefetched to avoid long memory fetch times after an instruction is executed. In one microprocessor, for example, the pipeline contains the next two sequential macro instructions or data words ahead of the current instruction being executed. A problem which arises when using a pipelined architecture is that during the execution of a store instruction the possibility exists that the data could be stored into a memory location which has already been loaded into the pipe. If a circuit is not provided to detect this condition, then the pipe must be reloaded every time a store instruction is executed. Depending upon how often store instructions are executed this could have a major impact on performance.