Browse Prior Art Database

NAND Decoder and Latch for Static RAM Decoder

IP.com Disclosure Number: IPCOM000039461D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Kroesen, PL MacFarland, JJ Mao, RS [+details]

Abstract

A low-power, high-speed decoder has been designed for a clocked field- effect transistor (FET) static random-access memory (RAM). The concept is based on an NAND configuration as opposed to the conventional NOR circuit and is applicable to N-type metal oxide semiconductors (NMOS). For large static RAMs the decoder power dissipation is the major contributor to the total RAM active as well as standby power consumption. As the speed and size of the RAMs increase, the slow speed of the decoder and its power consumption become significant drawbacks. (Image Omitted) An improved decoder circuit (Fig. 1) functions at low power and high speed and is based on the NAND configuration. With the conventional NOR circuit, all of the decoders, except the selected one, are drawing current and dissipating power.