Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
A multiplier-accumulate architecture is disclosed which is capable of being embodied on a single integrated circuit chip. Several integrated circuit chips with this architecture can be interconnected so that complex arithmetic operations can be performed, such as finite impulse response filtering and other digital signal processing operations. In the invention disclosed herein, a basic processing kernel architecture is shown in Fig. 1 which is embodied on a single integrated circuit chip, allowing a multiplicity of such single-chip processors to be interconnected in a time divided network for performing identical arithmetic operations in parallel on an input data stream, the results of which are merged on a time divided basis as filtered output data. The circuit of Fig.