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Improved Silicide Sub-Micron Fet Structure Disclosure Number: IPCOM000039467D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

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Gera, JS Shepard, JF [+details]


This article describes a reliable process for forming low resistance sub-micron polysilicon conductors while decreasing RIE (reactive ion etch) process uncertainties and bridging phenomena effects characteristic of the conventional processes. (Image Omitted) Fig. 1 illustrates in a cross-sectional view a conventional sidewall image transfer (SIT) process. Following completion of the SIT process, a sub-micron polysilicon line (gate) remains, as shown in Fig. 2. A layer of low temperature oxide (LTO) remains on top of the polysilicon line following completion of the polysilicon RIE process. Fig. 3 illustrates a further step in the process wherein an oxide is deposited over the line structure shown in Fig. 2.