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PLA Output Latch in TTL

IP.com Disclosure Number: IPCOM000039475D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

This article describes a means for obtaining increased performance of PLA (programmed logic array) output latches in TTL (transistor-transistor logic). TTL selector circuits are utilized for personality selection. By varying only the wiring configuration of the input control block, the latch can be configured in any of a number of desired latch types. (Image Omitted) Various configurations of output latches may be formed in PLA designs by wiring different logic functions to a pair of set/reset latches. Such functions include a gated data latch (GD), JK latch (JK) an AND latch (AB) and an Exclusive OR latch (XY). In conventional designs these personalities are realized by wiring different kinds of logic to a pair of "set/reset" latches as appear, for example, in Fig. 1A.