General-Purpose Interface Receiver for CMOS Technology
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
This CMOS Off-Chip receiver is capable of receiving low-level logic signals, where the Up-Level voltage is as low as 1.5 V. Standard TTL (transistor-transistor logic) receivers do not respond reliably to this Up-Level voltage. The TTL input transistor is configured to have high voltage gain, such that the output responds to the low-level input signal with minimum delay time. Input stage 1 is connected as a common gate transistor. When the input voltage 20 is at a Down-Level, transistor 1 conducts current from node 21 to node 20. This current discharges node 21 until its voltage is approximately equal to input voltage 20. This voltage at node 21 then turns P channel FET transistor 3 ON and N channel FET transistor 4 OFF, resulting in an Up-Level output voltage at output 22.