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Optimal Algorithm for Determining Channel Structure Placement of Circuit Chips

IP.com Disclosure Number: IPCOM000039482D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Luk, WK Sipala, P Tamminen, MI Wong, CK Woo, LS [+details]

Abstract

A technique is described whereby an algorithm is used to optimally determine the structural placement of channels for the automation of very large-scale integration (VLSI) circuit chip design. Methodology, based on slicing structures, is emphasized so as to efficiently utilize the empty space for channels and chip placement. The algorithm is used as a first step when determining the slicing structure of the placement, but is also applicable to arbitrary placements that are not slicing structures. (Image Omitted) In the physical design of a circuit chip, three elemental structural procedures are generally followed: 1) floorplanning, 2) global wiring, and 3) detailed wiring and layout of the macros.