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Optimal Algorithm for Determining Slicing Structure Placement of Circuit Chips

IP.com Disclosure Number: IPCOM000039485D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Luk, WK Sipala, P Tamminen, MI Wong, CK Woo, LS [+details]

Abstract

A technique is described whereby an algorithm is used to determine the maximal slicing structure of macro placements as used in the automation of very large-scale integration (VLSI) circuit chip design. The algorithm is designed to be computationally efficient, in that in any given placement defined only as a set of non-intersecting rectangular macros, the slicing structure can be determined and later applied to other physical design algorithms developed for slicing structures. (Image Omitted) In the physical design of a circuit chip, three elemental structural procedures are generally followed: 1) floorplanning, 2) global wiring, and 3) detailed wiring and layout of the macros.