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High-Bandwidth, Low-Contention, Hierarchical Memory Structure Disclosure Number: IPCOM000039505D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

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Lavallee, RW Ryan, PM Sollitto, VF [+details]


This hierarchical memory structure increases transfer bandwidth, greatly reduces contention, and allows much simpler memory management than can otherwise be achieved. Storage hierarchy performance can be dramatically improved by the application of the following concepts at one or more levels in the hierarchy: 1. A physical close-coupling of an adjacent pair of array levels to eliminate cables and to simplify the control structure. Higher performance due to a much wider inter-level bus, lower cost, and lower data management overhead are the advantages. The closest coupling and greatest bandwidth improvement are realizable when adjacent hierarchy levels are implemented on the same physical array chip. 2.