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Management of the RESET Tag to Accommodate Scanner Behavior in a Communication Controller Disclosure Number: IPCOM000039511D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

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Bersac, JM Laurent, B Pin, C [+details]


In a communication controller comprising a processor P connected to line scanners SC by bus B through a redrive circuit R, commands can be sent to processor P by a service processor SP through an address/command bus LAC (Fig. 1). The line scanners comprise a microprocessor which works under control of a microcode stored into a read-only memory (ROM). The B bus tag-out lines are used to send commands to the line scanners. Among these lines, a RESET tag is activated at the machine power-on to enable the ROM diagnostics. It is activated during the POWER-ON RESET time signal which is sent to P by a line coming from the service processor. Processor P is designed according to the level sensitive scan design (LSSD) technique, and thus comprise LSSD shift register chains which may be loaded from the service processor.