Overlapped Clock Mechanism to Reset Control Signal
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
The use of branches in a pipelined system causes many problems with synchronizing instructions and also causes degradations in performance. The reason for this is because by the time a branch is detected by the processor, the instruction pipeline unit has already started to fetch the next instruction. Generally this would not cause much of a delay unless fetching the next instruction is complicated for some reason, such as requiring a main storage access. Because accessing main storage is typically very slow compared to instruction execution, and the instruction being fetched is not going to be used because of the branch, performance is affected. Even if the storage operation could be canceled after it has started, it would still be necessary to re- synchronize before fetching the target of the branch.