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Primary Error Detection System for I/O Apparatus

IP.com Disclosure Number: IPCOM000039523D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Bell, BC Kinter, HB Westcott, GR [+details]

Abstract

In a distributed processor control unit architecture for line printers and other I/O machines, a main processor supervises separate controls or controllers provided for each of the different sectors of the machines, e.g., paper feed carriage, type band drive, and hammer firing logic circuitry. In such an environment, error detection and follow-on problem determination and resolution is complicated. The solution is provided by circuitry which detects and identifies the first or primary error and blocks interference from secondary errors. As shown in the figure, an Error Set signal from the error detection logic 10 of a machine sector sets an appropriate latch 11 of error register 12.