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Browse Prior Art Database

New Configuration of CMOS-DOMINO Logic

IP.com Disclosure Number: IPCOM000039532D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Oklobdzija, VG [+details]

Abstract

This article describes a circuit configuration that has all of the advantages of a CMOS-DOMINO circuit family, yet it assures consistent precharge and is "glitch-free". The structure to be used as a CMOS-DOMINO logic block has all of the advantages of CMOS-DOMINO logic as described in [*]. The function of this logic complies with all restrictions imposed on CMOS-DOMINO (no inversion possible) and has all the benefits of this logic: CMOS power requirements and speed of dynamic n-MOS logic. However, this logic family is "glitch-free", i.e., functional block f is fully precharged during each precharge period so that during the "evaluation" phase the node F (Fig.