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Dual Hardware Buffer for Video Display

IP.com Disclosure Number: IPCOM000039539D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Kirk, CR [+details]

Abstract

This article describes an apparatus that allows the data being displayed on a monitor to be changed in constant time independent of the amount of data being changed and in a short enough time to prevent blinking of the screen. The device uses two hardware buffers in the video adapter for controlling display on the screen. The hardware buffers are controlled so that when data is being loaded into one, information for refreshing the display is being extracted from the other buffer. In the figure, a 2k RAM is used for both buffers. The high-order address bit for the refresh address is a complement for the write address. Thus, half the RAM is the refresh buffer, while the other half is a write buffer. The buffer select line is toggled by system software (not shown) causing the buffers to swap roles.