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HARDWARE RETRY MECHANISM for MULTISTAGE INTERCONNECTION NETWORKS for PARALLEL COMPUTERS

IP.com Disclosure Number: IPCOM000039542D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
George, DA Goyal, A Jackson, RD Kumar, M Rathi, BD [+details]

Abstract

Multistage Interconnection Networks (MINs) used in parallel computers transmit one word at a time between stages of switches. The size of these words depends on the implementation of the network. In order to implement data retry across long links in a network, the transmitting logic of the switch, attached to this link, should be able to buffer more than one word that has been transmitted across the link. The length (i.e., number of words) of this buffer depends on: the maximum number of bits that can be carried by a wire of the link at any point in time, the delay in the receiving logic to detect an error, and the delay in the transmitting logic to detect that retry is requested. Let "k" be the maximum number of bits a wire of the long link can carry at any point in time.