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Dynamic Ram Address Relocation Circuit

IP.com Disclosure Number: IPCOM000039555D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01

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Related People

Anderson, KL Ellenberger, AR Ellis, WF Streck, JP [+details]


For the purpose of address translation and part number reduction in a partially good random-access memory program, an address buffer and associated address relocation memory is featured. The address buffer is composed of an input latch 10 which provides selected switchable complementary output signals. These latch output signals are coupled through a pair of transfer devices 11 and 12, controlled by non-volatile fault location address circuits 13 and 14. The outputs of devices 11 and 12 are coupled to nodes N10 and N20 which are cross-coupled to sets of devices 15 and 16 and 17 and 18 which provide true (T) and complementary (C) address signals to drive the memory address decoders (not shown).