Current Sense Static Bipolar Random-Access Memory Cell
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
In this current sense cell, sensing and writing is done through two NPN transistors added to a basic complementary transistor switch (CTS) latch. These two NPN transistors, serving as the bit line interface, are formed in existing P-type regions by the addition of an N+ emitter diffusion. The resulting random-access memory (RAM) cell has improved access time, requires smaller power supply voltage differential (Vhigh - Vlow), and has improved alpha particle immunity. The CSC cell is shown in the figure. The cell utilizes transistors 3, 4, 5, and 6 to form the basic (CTS) latch. NPN transistors 1 and 2 have been added to serve as the bit line interface. A word line WL is selected by pulling it up by approximately 300 mV while simultaneously increasing the current. The same procedure is used for both read and write operations.