Browse Prior Art Database

Enhancement of Memory Card Redundant Bit Usage Via Simplified Fault Alignment Exclusion Implementation

IP.com Disclosure Number: IPCOM000039575D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Arlington, DL Evans, EK [+details]

Abstract

A method is described for enhancing redundancy at the card level by providing a plurality of registers such that one redundant bit can replace bits in any of "n" chips. The advantage of this method over previous card level redundancy techniques is that more than one chip failure per chip level can be accommodated. Memory cards are often expanded by adding banks of memory modules or chips having input/output (I/O) lines dotted to I/O of previous banks or levels. This is illustrated in Fig. 1 wherein the top row represents the base card, e.g., a 4-byte-wide bank, 256 bit chips, one chip deep, thus providing a one-megabyte card. A 2x expansion is obtained by adding another bank of chips with input/output (I/O) dotted to the first bank. By adding two more banks, 4 megabytes with each bit 4 chips deep is obtained.