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New Context Bit Disclosure Number: IPCOM000039576D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01

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Emma, PG Knight, JW Pomerene, JH Rechtschaffen, RN Sparacio, FJ [+details]


The present invention proposes a new context bit to initiate sequential prefetching of instruction lines. This helps minimize misses for sequential instruction lines when a new context is encountered in the execution of instructions. When a processor begins to execute a sequence of instructions that have not been executed in a long time, many of the instruction lines that are about to be used will not be in the cache. Most instruction reference patterns display strong sequentiality, i.e., if a line is referenced, it is very likely that the next sequential line will also be referenced by the processor for the purpose of fetching instructions. A cache may be considered to contain a collection of recently executed contexts with their most recently executed lines.