Dismiss
The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Random Pattern Testability of the Logic Surrounding Memory Arrays

IP.com Disclosure Number: IPCOM000039582D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Bardell, PH Gupta, VP McAnney, WH Ratiu, IM Savir, J [+details]

Abstract

The cutting algorithm 1 may be used in computing a lower bound of the detection probability of faults surrounding memory arrays. If the array and the logic surrounding it are such that there is a complete isolation between the control address logic, the prelogic and the postlogic (see Fig. 1), then the probability that a sequence of length M will detect a fault in either the prelogic or the postlogic is given by where L is the number of fresh reads, and pr is the restricted exposure probability. The restricted exposure probability can be computed by removing the array, and connecting the prelogic and postlogic together (see Fig. 1). This transform leads to a combinational logic for which several existing algorithms may be used.