Browse Prior Art Database

Round Robin Control Hardware

IP.com Disclosure Number: IPCOM000039599D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Higgins, SR [+details]

Abstract

In a multiprocessor system in which a plurality of processors share a single bus, round robin control hardware operates in either of two modes. The first mode varies the processor priorities on a round robin basis so that each processor has equal access to use of the bus over a period of time. In the second mode, the processors, through hardwiring, are assigned permanent priorities. (Image Omitted) Fig. 1 is a schematic diagram of a multiprocessing system in which a plurality of processors P1-Pn are connected to a common bus 10. Each processor includes round robin control hardware 12, the general details of which are shown schematically in Fig. 2. Within the system, each processor has its own hardwired slot id (SID).