SCHEME for REDUCING CLOCK SKEW in MULTIPLE-CHIP SYSTEM DESIGN
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
In multiple-chip implementation of high-performance systems with very short clock cycle, say below 20 nanoseconds, the design approach to avoid clock skew is crucial. Since the on-chip clock loading can be very heavy in the VLSI environment, the on-chip clock re-drive and distribution are unavoidable. Under this circumstance, clock skew can (Image Omitted) come from two sources. One is intra-chip (local) clock interconnection/distribution and the other is inter-chip (global) clock interconnection/distribution. The intra-chip clock skew can be controlled fairly well by a chip designer by using balanced clock distribution network with matched transmission line interconnection. The clock is distributed within a chip in such a way that at each node of distribution the clock is equally delayed from the clock input.