Method for Minimizing Critical Timing of a Digital System
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
A technique is described whereby the critical delay timings of logic circuits, as used in digital computer systems, are minimized by synthesizing the logic in a hierarchical manner. Since input signals arrive at different times and the outputs are required at different times, logic blocks (macros) are re-synthesized along the systems critical timing paths. This method, when used in conjunction with other techniques, decreases the overall delay of the logic flow. Since each logic block of a digital system contains a number of inputs and outputs, the system can be viewed as a direct graph where each node is a logic block. A branch is drawn from node i toward node j if one of the outputs of node i is a primary input for node j. It is then assumed that the graph is acyclic.