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High-Speed Medium-Power Ttl-To-Ecl I/O Translator Circuit With Level Lifting

IP.com Disclosure Number: IPCOM000039611D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Davis, JD Pritzlaff, PE Wolf, RE [+details]

Abstract

This article describes a circuit that translates level shifted TTL (transistor-transistor logic) to ECL (emitter-coupled logic) levels in a high performance machine. The disclosed circuit was designed to interface an ECL "ground centered system" chip with a TTL typically "above-ground system" chip which will use the "around ground supplies" in a high end computer. The circuit (see figure) functions in down-level, up-level and high impedance states as follows: Down Level: Transistor T1 pulls node N2 LOW when the input node IN is low (N1 < -1.8 volts), turning T2 OFF. With T2 OFF, node N4 is pulled UP by resistor R3 and Schottky diodes SB1 and SB2. With node N4 HIGH, T4 turns ON, turning OFF T5. Meanwhile, node N8 is pulled LOW, turning the output transistor pair T7 and T8 OFF.