IMPROVED DECODE CIRCUITS for CMOS MEMORY ARRAYS
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
A novel memory address decode circuit with precharge support circuits integrated into a decoder design for CMOS memory arrays is described. Charge distribution is a problem in NAND decoders utilized in some CMOS memory products. The self-clocking precharge scheme disclosed eliminates precharge distribution and guarantees that selected address lines are switched only when the decoder outputs are valid. (Image Omitted) The address decoder circuit in Fig. 1 normally drives only one of four select lines when clock is high. It is also utilized for precharge distribution by selecting all four select lines when clock is low.