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Microcoded Self Exerciser

IP.com Disclosure Number: IPCOM000039648D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Fidishun, PD [+details]

Abstract

This article presents a method of testing a Writable Control Storage (WCS) array. The technique uses combinations of valid microcode words to exercise the entire WCS in an operational environment. The test is conducted at full machine speed exercising a WCS address each machine cycle. It uses the built-in error detection schemes of WCS parity and sequence checking to detect and report faults. Failure isolation is enhanced down to the chip level with the aid of the Processor Controller (PC) and Trace arrays. In the design, the time required to conduct the test is minimized, and the PC code required to support the exerciser is also minimized. The WCS is tested by using operationally valid micro-words for patterns and existing Parity and Sequence checks to report errors.