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Logic-Level Testing of CMOS Switching Capacitors

IP.com Disclosure Number: IPCOM000039660D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Woodman, GR [+details]

Abstract

A test path for all digital testing of switched capacitors circuits is proposed. Switched capacitors are used as adjustment elements in digitally-controlled circuit path delays. Typically, analog testing is required since there is no change in the logic level or logical function of such paths when delays are switched in and out of the path. The present method obviates the need for non-automated analog testing of CMOS switched capacitor elements. Using only logic levels, the proposed method verifies that each device exists in the network. Referring now to the figure, a basic testable switched capacitor delay path is shown. In the operational state, the Test Control Node E is held positive to turn on the large n-channel device "I", which effectively grounds both sides of the capacitor devices A - H.