Fuse Circuit With Zero DC Current
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
A fuse circuit for embedded arrays with word line redundancy is described which provides DC voltage levels V0 = 0V, VH but draws no DC current. This feature is essential as it ensures that leakage current measurements, which are a simple first test for CMOS logic chips, are not falsified by the fuse circuit. The figure shows the circuit which consists of a set driver, a coupling capacitor CC, a fuse, and a latch. The set driver generates a rising voltage VS which is derived from the rising power supply signal VH during power-on. Voltage VS is coupled by capacitor CC to the latch, setting it to the "0" state (output voltage V0 = 0V) if the resistance of the fuse is high (fuse blown or cut). If the resistance of the fuse is low (fuse not blown), the latch goes to the "1" state (V0 = VH).