CMOS Driver Circuit
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01
This circuit is an interface to CMOS chips that may provide a down level of voltage from 0 to .5 volts and an up level ranging from 1.55 to 2.2 volts, the latter being a rather unusual voltage range, while providing good response time and stability while driving transmission lines with various kinds of loading conditions. The circuit enables slew rate limiting and feedback in an off chip driver and may be incorporated in a CMOS I/O BUS tri-state driver. The circuit is composed of N-channel standard threshold devices (Q2, Q6, Q7, Q8, Q10, Q11, Q13, Q27, Q28), N-channel low threshold devices (Q17- Q26), and P-channel standard threshold devices (Q1, Q3-Q5, Q9, Q12, Q14-Q16). The circuit has the signal input A0; tri-state enables B0 and DI (data inhibit), and output P10.