Browse Prior Art Database

Multi-Technology Chip Carrier

IP.com Disclosure Number: IPCOM000039677D
Original Publication Date: 1987-Jul-01
Included in the Prior Art Database: 2005-Feb-01

Publishing Venue

IBM

Related People

Authors:
Butz, M Dao Trong, S Hinrichsmeyer, K Stadler, EE [+details]

Abstract

The chip carrier comprises a multilayer ceramic base carrier 1 on which a multilayer flexible polyimide carrier 2 is deposited. Chips 3 are connected to flexible carrier 2 by C4 connections 5. Ceramic carrier 1 comprises power distribution layers 6 (sandwich power plane structure). Conductive layers 7 of carrier 2 contain the entire chip-to-chip and off module signal wiring. Interconnections are made by vias 8. Power interconnection pins 9 are soldered to a card or board (not shown). Flexible carrier 2 extends beyond the sides of ceramic carrier 1, which may be provided with external connections. The advantages are as follows: - A low-cost ceramic carrier may be used. Only power distribution layers are required, so that the top surface has the most critical reference layer.